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Title
Address
Department
Date
Front End Design Engineer
Hangzhou/Phoenix
Product Technology
2018-07-24

Requirements

  • Master’s degree in Electrical/Computer Engineering, with 5+ years of industry experience in ASIC frontend development.

  • Proficiency with Verilog & System Verilog RTL coding and verification

  • Proficiency with low power digital design techniques

  • Proficiency with synthesis and static timing

  • Proven track record with writing detailed test plans

  • Strong FPGA platform-based development and testing experience

  • Problem solving skills and out-of-the-box thinking to test and validate hardware

  • Collaboration in a group environment while still being able to contribute on an individual basis

  • Strong communication skills, both verbal and written

     

    Responsibilities

    1. Implement assigned design modules in Verilog and System Verilog RTL

    2. Run simulation to verify RTL code

    3. Script executive and constraints for Synthesis and Timing check  

    4. Conduct formality check

    5. Analyze clock domain crossing rules

    6. Develop system testing and debug using FPGAs

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SoC Architecture
Hangzhou/Phoenix
Product Technology
2018-07-24

Requirements:

  • Knowledgeable with the ArmV8 architecture, including the new 64-bit support and new architectural features. Must possess an understanding of the Symmetrical Multiprocessing (SMP) concept and its usage in the Arm implementations.

  • Must have working knowledge of AMBA interconnect protocol, specifically AHB, AXI and cache coherent support at the protocol and SoC architecture/micro-architecture levels.  

  • Have an understanding of the overall Arm-based system architecture and applications behavior, software/hardware co-design synergy, power on reset/boot-up sequencing and firmware support requirements.

  • Experience in the DDR or LPDDR memory subsystem architecture and design is extremely valuable.

  • Knowledgeable in the imaging and display subsystems is a plus.

  • Possess RTL-level design experience using Verilog and system Verilog, with an understanding of FPGA implementation intricacies a plus.

  • Understand C/C++ designs and validation infrastructure to help guide pre-/post-silicon software and validation activities.

  • Can conduct system/SoC-level performance and power analysis/trade-offs and optimizations.

  • Understand high-speed design and pipelining techniques is a must.

  • Knowledgeable in design for reliable and secured systems and SoCs would be highly desirable.

  • Ability to collaborate and work across multiple teams and disciplines is a must.

  • Master degree in Electrical or Computer Engineering with 10+ years of experience or a Ph.D. degree in Electrical or Computer Engineering with 5+ years of experience is required.

 

Responsibilities:

  • The successful candidate will be a member of the products architecture team, participate in the products definition, help define/spec new product features inclusive of performance, reliability, and debug/test requirements.

  • Write architecture/micro-architecture specifications. Participate in design and validation test plan reviews.

  • Perform performance and power analysis and provide optimization trade-offs.

Work closely with verification and design teams to ensure re-usability across products generations and high level of products quality.  

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Physical Design Engineer
Hangzhou/Phoenix
Product Technology
2018-07-24

Requirements

  • Master’s degree in Electrical/Computer Engineering, with 5+ years of industry experience in design, implementation and verification of ASICs

  • Strong communication skills, both verbal and written

  • Proficiency with low power digital design techniques

  • Must be proficient in ICC2.

  • Must be highly skilled in at least one of the following areas: PnR, synthesis, STA, RedHawk EM/IR and ICV/Calibre LVS/DRC.

  • Must be proficient in TCL and Linux.

 

  • Collaboration in a group environment while still being able to contribute on an individual basis.

  • Experience with TSMC 28nm design is a plus.

 

 

Responsibilities

  1. Own a block or SOC for synthesis and PnR.

  2. Own a back-end tool which includes flow, methodology development and execution.

  3. Cover team member on other backend activities.

  4. Participate in chip development planning and scheduling.

Apply

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Xihu District, Hangzhou, Zhejiang.      

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